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CXD2309Q
10-bit 85MSPS 3-Channel D/A Converter
Description The CXD2309Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel input/output. This is ideal for use in high-definition TVs and high-resolution displays. Features * Resolution 10-bit * Maximum conversion speed 85MSPS * RGB 3-channel input/output * Differential linearity error 0.5 LSB * Low power consumption 275 mW (200 load for 2 Vp-p output) * Single +5 V power supply * Low glitch * 48-pin QFP package Structure Silicon gate CMOS IC 48 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage AVDD, DVDD 7 V * Input voltage (All pins) VIN VDD+0.5 to VSS-0.5 V * Output current IOUT 0 to 15 mA * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 DVDD, DVSS 4.75 to 5.25 * Reference input voltage VREF 0.5 to 2.0 * Clock pulse width TPW1, TPW0 9 (min.) * Operating temperature Topr -20 to +85
V V V ns C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E94341B01
CXD2309Q
Block Diagram
(LSB) R0 R1 R2 R3 R4 R5
1 2 3 4 5
DECODER LATCHES
4LSB'S CURRENT CELLS
43 AVSS 42 RO
6 R6 7
R7 R8
6LSB'S CURRENT CELLS
8 9
DECODER CLOCK GENERATOR
(MSB) R9 10 RCK 31 (LSB) G0 11 G1 12 G2 13 G3 14 G4 15 G5 16 G6 17 G7 18 G8 19 (MSB) G9 20 GCK 32 (LSB) B0 21 B1 22 B2 23 B3 24 B4 25 B5 26 B6 27 B7 28 B8 29 (MSB) B9 30 BCK 33 DVDD 48 BIAS VOLTAGE GENERATOR DECODER DECODER LATCHES DECODER DECODER LATCHES
4LSB'S CURRENT CELLS
45 AVSS 44 GO
6LSB'S CURRENT CELLS
CLOCK GENERATOR
4LSB'S CURRENT CELLS
47 AVSS 46 BO
6LSB'S CURRENT CELLS
41 AVDD 40 AVDD 39 AVDD
CLOCK GENERATOR 38 VG CURRENT CELLS (FOR FULL SCALE) 37 VREF 36 IREF
VB 35 DVSS 34
--2--
CXD2309Q
DVSS
IREF
BCK
VB
B9 (MSB)
Pin Configuration
GCK RCK
B5
26
B8
B7
36 VREF 37 VG 38 AVDD 39 AVDD 40 AVDD 41 RO 42 AVSS 43 GO 44 AVSS 45 BO 46 AVSS 47 DVDD 48
35
34
33
32
31
30
29
28
27
B6
25 24 B3 23 B2 22 B1 21 B0 (LSB) 20 G9 (MSB) 19 G8 18 G7 17 G6 16 G5 15 G4 14 G3 13 G2
1
(LSB) R0
2
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
11
12
(LSB) G0
(MSB) R9
G1
B4
1
to
35 , 48
Digital system
36 to 47 Analog system
Pin Description and Equivalent Circuit Pin No. 1 to 10 Symbol R0 to R9 I/O Equivalent circuit Description Digital input. 1 pin R0 (LSB) to 10 pin R9 (MSB) 11 pin G0 (LSB) to 20 pin G9 (MSB) 21 pin B0 (LSB) to 30 pin B9 (MSB)
11 to 20 G0 to G9 21 to 30 31 32 33 34 B0 to B9 RCLK GCLK BCLK DVSS --
DVDD
I
1 to 33
DVSS
Clock input.
Digital ground.
DVDD
DVDD
35
VB
O
35
Connect an approximately 0.1F capacitor.
DVSS
--3--
CXD2309Q
Pin No.
Symbol
I/O
Equivalent circuit
Description Reference current output. Connect an "RIR" resistor which are 16 times the output resistance "ROUT".
36
IREF
O
AVDD
AVDD
36 AVDD AVDD AVSS 37 38 AVSS
37
VREF
I
Reference voltage input. Sets an output full-scale value.
38
VG
O
AVSS
Connect an approximately 0.1F capacitor.
39 to 41 42
AVDD RO
--
AVDD 42 44
Analog power supply.
44
GO
O
46 AVSS
Current output. Output can be obtained by connecting a resistor (200 typ.).
AVSS
46 43, 45, 47 48
BO AVSS DVDD -- --
Analog ground. Digital power supply.
--4--
CXD2309Q
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale ratio 1 Output full-scale current Output offset voltage Glitch energy Crosstalk SN ratio Supply current Analog input resistance Input capacitance Output capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time Rise time Fall time 1
(fCLK=85 MHz, AVDD=DVDD=5 V, ROUT=200 , VREF=2.0 V, RIR=3.3 k, Ta=25C) Symbol n fCLK EL ED VOC VFS FSR IFS VOS GE CT SNR IDD RIN CI CO VIH VIL IIH IIL ts th tPD tr tf Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +85 C Endpoint Min. Typ. 10 Max. Unit bit MSPS LSB LSB V V % mA mV pV*s dB dB 58 mA M pF pF V A ns ns ns ns ns
0 -2.0 -0.5 1.8 1.8 0 9.0 1.92 1.92 9.6 50 42 40 55 50 48 55
85 2.0 0.5 2.0 2.0 3 10 1
When "0000000000" data input ROUT=100 , 1 Vp-p output When 10 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 1 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 10 MHz FCLK=50 MHz sin wave output FCLK=85 MHz VREF
40 50
1 9 125
AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C
2.15 0.85 -5 4 1 14 26.5 26.0 x 100 (%) 5
Full-scale output ratio =
Full-scale voltage of channel -1 Average of the full-scale voltage of the channels
Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current
}
+5.25V
AVDD, DVDD
A
CXD2309Q
V
AVSS, DVSS
--5--
CXD2309Q
Conversion Rate Measurement Circuit
R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 35 VB 0.1 DVSS CLK 50MHz SQUARE WAVE 31 RCK 32 GCK 33 BCK AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1 AVSS 45 BO 46
10bit COUNTER with LATCH
200 AVSS OSCILLOSCOPE 200 AVSS 200 AVSS AVDD
Setup Time Hold Time Glitch Energy
}
Measurement Circuit
10bit COUNTER with LATCH 35 DELAY CONTROLLER 0.1 DVSS
R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 21 to 30 GO 44 VB AVSS 45 BO 46 31 RCK AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1
200 AVSS OSCILLOSCOPE 200 AVSS 200 AVSS AVDD
CLK 50MHz SQUARE WAVE
32 DELAY CONTROLLER
GCK
33 BCK
Crosstalk Measurement Circuit
DVDD DIGITAL WAVEFORM GENERATOR 35 0.1 DVSS 31 RCK CLK 50MHz SQUARE WAVE 32 GCK 33 BCK R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 21 to 30 GO 44 VB AVSS 45 BO 46 AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1 200 AVSS 200 AVSS 200 AVSS AVDD SPECTRUM ANALYZER
--6--
CXD2309Q
DC Characteristics Measurement Circuit
R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 35 VB 0.1 DVSS CLK 50MHz SQUARE WAVE 31 RCK 32 GCK AVSS 45 BO 46 AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1
200 AVSS DVM 200 AVSS 200 AVSS AVDD
CONTROLLER
33 BCK
Propagation Delay Time Measurement Circuit
10bit COUNTER with LATCH R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 35 VB 0.1 DELAY CONTROLLER CLK 50MHz SQUARE WAVE DVSS 31 RCK 32 DELAY CONTROLLER GCK AVSS 45 BO 46 AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1
200 AVSS OSCILLOSCOPE 200 AVSS 200 AVSS AVDD
33 BCK
SNR Measurement Circuit
DIGITAL WAVEFORM GENERATOR
ALL "1"
ALL "1"
R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 35 VB 0.1 AVSS 45 BO 46 31 RCK AVSS 47 VG 38 VREF 37 2V IREF 36 3.3k AVSS 0.1
200 AVSS 200 AVSS 200 AVSS AVDD SPECTRUM ANALYZER
DVSS CLK 50MHz SQUARE WAVE 32 GCK 33 BCK
--7--
CXD2309Q
Description of Operation Timing Chart
tPW1 tPW0
CLK
1.5V
ts th
ts th
ts th
DATA
1.5V
100% 90%
D/A OUT tPD tr tf
50% 10% 0%
I/O Correspondence Table (output full-scale voltage: 2.00 V) Input code Output voltage MSB LSB 1111111111 2.0 V : 1000000000 1.0 V : 0000000000 0V
--8--
CXD2309Q
Notes on Operation * Selecting the Output Resistance CXD2309Q is a current output type D/A converter. The output voltage can be obtained by connecting the resistor ROUT to the current output pins RO, GO and BO. Specifications: Output full-scale voltage VFS = 1.8 to 2.0 [V] Output full-scale current IFS = 9.0 to 10.0 [mA] Calculate the output resistance from VFS = IFS x ROUT. Connect a resistance sixteen times the output resistance to the reference current output pin IREF. In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following. VFS = VREF x 16ROUT/RIR VREF is the voltage set at the reference voltage input pin VREF, ROUT is the resistor to be connected to the current output pins RO, GO, BO and RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data setting time. Set the best values according to the purpose of use. * Correlation between Data and Clock For CXD2309Q to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in "Electrical Characteristics". * Power supply, ground Separate the analog and digital signals around the device to reduce noise effects. Bypass the power supply pin to each ground with a 0.1 F ceramics capacitor as near as possible to the pin for both the digital and analog signals. * Latch up Analog and digital power supplies must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. * IREF The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. * VG pin It is recommended to use a 1 F capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1 F. * Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the RO, GO and BO output full-scale voltages are used with not adjustment.
--9--
CXD2309Q
Application Circuit
C
C
R2
Clock input
36 R3 37 R4 C C C 38 39 40 41 42 R1 43 44 R1 45 46 R1 47 48
35
34
33
32
31
30
MSB
29
28
27
26
25 24 23 22 21 20 19 18 17 16 15 14 13 G ch input LSB MSB B ch input
1
LSB
2
3
4
5
6
7
8
9
10
11
12
R ch input
AVDD
DVDD
AVSS
DVSS
* * * * * *
When the power supply (AVDD and DVDD) is 5.0 V. R1=200 R2=3.3 k R3=3.0 k R4=2.0 k C=0.1 F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--10--
MSB
LSB
CXD2309Q
Latch Up Prevention The CX2309Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pin 39, 40 and 41) and DVDD (Pin 48), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD 39 40 AVDD +5V +5V C CXD2309Q C DIGITAL IC 41 48 DVDD
AVSS 43 AVSS 45 47
DVSS 34
b. When analog and digital supplies are from a common source (i)
DVDD
39
40 AVDD
41
48 DVDD
+5V C CXD2309Q C DIGITAL IC
AVSS 43 AVSS 45 47
DVSS 34
(ii)
DVDD
39
40 AVDD
41
48 DVDD
+5V C CXD2309Q C DIGITAL IC
AVSS 43 AVSS 45 33 47
DVSS 34 31
--11--
CXD2309Q
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 39 40 AVDD +5V +5V C CXD2309Q C DIGITAL IC 41 48 DVDD
AVSS 43 AVSS 45 47
DVSS 34
b. When analog and digital supplies are from common source (i)
DVDD AVDD 39 40 AVDD +5V C CXD2309Q C DIGITAL IC 41 48 DVDD
AVSS 43 AVSS 45 47
DVSS 34
(ii)
DVDD AVDD 39 40 AVDD +5V CXD2309Q C DIGITAL IC 41 48 DVDD
AVSS 43 AVSS 45 47
DVSS 34
--12--
CXD2309Q
Example of Representative Characteristics
Output full-scale voltage VFS [V]
2.0
1.0
Glitch energy GE [pV*s]
0 1.0 2.0
100
50
0
100
200
Reference voltage VREF [V] Fig. 1. Reference voltage vs. Output full-scale voltage
Output resistance ROUT [] Fig. 2. Output resistance vs. Glitch energy
70
Output full-scale voltage VFS [V]
1.95
Supply current IDD [mA]
sin wave output 60
1.90
50
V=0.02mV/C 0
40
-25
0
25
50
75
12
5
10
20
30
40 42
Ambient temperature Ta [C] Fig. 3. Ambient temperature vs. Output full-scale voltage
Output frequency Fo [MHz] Fig. 4. Output frequency vs. Supply current
Standard Measurement Conditions * AVDD=DVDD=5.0 V * VREF=2.0 V * FCLK=85 MHZ * ROUT=200 * RIR=3.3 k * Ta=25 C
--13--
CXD2309Q
60
fout=1MHz sin wave
60
fout=10MHz sin wave IDD
Supply current IDD [mA]
50 IDD 40 IA [Analog] 30 20 10 20 ID [Digital] 50 85
Supply current IDD [mA]
50 40
IA [Analog] 30 20 ID [Digital] 10 20 50 85
Clock frequency FCLK [MHz] Fig. 5. Clock frequency vs. Supply current
Clock frequency FCLK [MHz] Fig. 6. Clock frequency vs. Supply current
60
Cross talk CT [dB]
40 30 20 10 0 1 2 5 10 20 42
Output level [dBm]
50
sin wave output
0
-10
-20
0
1
2
5
10
20
50
Output frequency Fo [MHz] Fig. 7. Output frequency vs. Cross talk
Output frequency Fo [MHz] Fig. 8. Output frequency vs. Output level (Including primary hold characteristics sinx/x)
Standard Measurement Conditions * AVDD=DVDD=5.0 V * VREF=2.0 V * FCLK=85 MHZ * ROUT=200 * RIR=3.3 k * Ta=25 C
--14--
CXD2309Q
50
1000
40
Input current [A]
SNR [dB]
500
30
0
1
2
5
10
20
50
-1
0
1
5
6
Output frequency Fo [MHz] Fig. 9. Output frequency vs. SNR 500
Input voltage [V]
1000
Fig. 10. Input terminal V-I characteristics
Standard Measurement Conditions * AVDD=DVDD=5.0 V * VREF=2.0 V * FCLK=85 MHZ * ROUT=200 * RIR=3.3 k * Ta=25 C
--15--
CXD2309Q
Package Outline
Unit : mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05 0.15 36 25
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.24
M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g
--16--
0.9 0.2
13.5

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